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(2002)Conference PaperCurrent FPGA design flows do not readily support high-level, behavioural design or the use of run-time reconfiguration. Designers are thus discouraged from taking a high-level view of their systems and cannot fully exploit the benefits of programmable hardware. This paper reports on our advances towards the development of design technology that supports behavioural specification and compilation of FPGA designs and automatically manages FPGA chip virtualization.
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(2002)Conference PaperWe propose to modify a type of ant algorithm called Population based Ant Colony Optimization (P-ACO) to allow implementation on an FPGA architecture. Ant algorithms are adapted from the natural behavior of ants and used to find good solutions to combinatorial optimization problems. General layout on the FPGA and algorithmic description are covered. The most notable achievements featured in this paper are a runtime reduction and including the approximation of the heuristic function by a small set of favored decisions which changes over time.
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(2002)Conference PaperThe Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned, synthesised, and mapped to pre-allocated resources, in this system the specified circuits are extracted from behavioural specifications that are partitioned, elaborated, mapped, and configured at run time as control passes through them. We report on the details of a design that targets the Celoxica RC1000 co-processor and assess preliminary performance results for this implementation. The results clearly demonstrate our method is a practical approach to overcome resource constraints, particularly in applications where these change at run time. The results also establish a benchmark against which to measure future improvements and alternative methods.
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(2002)Conference PaperThis paper describes the design of an interpreter that overcomes FPGA resource limitations for a class of control-oriented circuits by automatically partitioning, elaborating, and loading circuit components as directed by their execution. By providing a virtual hardware management facility, this enables us to implement large systems, specified in Circal, on small FPGA chips.
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(2001)Conference PaperModularity is a key aspect of system design, particularly in the era of system-on-chip. Field-programmable logic (FPL), particularly with the rapid increase in programmable gate counts, is a natural medium to host run-time modularity, that is, a dynamically-varying ensemble of circuit modules. Prior research has presumed the use of an external processor to manage such an ensemble. In this paper, we consider on-chip management, implemented in the FPL itself, based upon a one-dimensional allocation model. We demonstrate an algorithm for on-chip identification of free FPL resource for modules, and an approach to on-chip rearrangement of modules. The latter includes a proposal for a realistic augmentation to existing FPGA reconfiguration architectures. The work represents a key demonstration of how FPL can be used as a first-order computational resource, rather than just as a slave to the microprocessor.
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(2000)Conference PaperHigh-level, behavioural language specification is seen as a significant strategy for overcoming the complexity of designing useful and interesting reconfigurable computing applications. However, appropriate frameworks for the design of behaviourally specified systems are still being sought. We are investigating behavioural language and compiler design based on the Circal process algebra, which is a natural framework within which to describe the concurrent activity of reconfigurable logic circuits. In this paper we describe an FPGA interpreter that exploits the inherent concurrency, hierarchy, and modularity of Circal and its circuit realization to automatically manage hardware virtualization. The techniques employed by the interpreter may be used to overcome resource limitations and adapt circuits to changing application needs at run time.
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(2001)Journal ArticleThe development of FPGAs that can be programmed to implement custom circuits by modifying memory has inspired researchers to investigate how FPGAs can be used as a computational resource in systems designed for high performance applications. When such FPGA--based systems are composed of arrays of chips or chips that can be partially reconfigured, the programmable array space can be partitioned among several concurrently executing tasks. If partition sizes are adapted to the needs of tasks, then array resources become fragmented as tasks with varying requirements are processed. Tasks may end up waiting despite their being sufficient, albeit fragmented resources available. We examine the problem of repartitioning the system (rearranging a subset of the executing tasks) at run--time in order to allow waiting tasks to enter the system sooner. In this paper, we introduce the problems of identifying and scheduling feasible task rearrangements when tasks are moved by reloading. It is shown that both problems are NP--complete. We develop two very different heuristic approaches to finding and scheduling suitable rearrangements. The first method, known as Local Repacking, attempts to minimize the size of the subarray needing rearrangement. Candidate subarrays are repacked using known bin packing algorithms. Task movements are scheduled so as to minimize delays to their execution. The second approach, called Ordered Compaction, constrains the movements of tasks in order to efficiently identify and schedule feasible rearrangements. The heuristics are compared by time complexity and resulting system performance on simulated task sets. The results indicate that considerable scheduling advantages are to be gained for acceptable computational effort. However, the benefits may be jeopardized by delays to moving tasks when the average cost of reloading tasks becomes significant relative to task service periods. We indicate directions for future research to mitigate the cost of moving executing tasks.
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(2001)Journal ArticleReconfigurable computers based on field programmable gate array technology allow applications to be realised directly in digital logic. The inherent concurrency of hardware distinguishes such computers from microprocessor-based machines in which the concurrency of the underlying hardware is fixed and abstracted from the programmer by the software model. However, reconfigurable logic provides us with the potential to exploit `real` concurrency. It is therefore interesting to know how to exploit this concurrency, how to model concurrent computations, and which languages allow this dynamic hardware to be programmed most effectively. The purpose of this work is to describe an FPGA compiler for the Circal process algebra. In so doing, the authors demonstrate that behavioural descriptions expressed in a process algebraic language can be readily and intuitively compiled to reconfigurable logic and that this contributes to the goal of discovering appropriate high-level languages for run-time reconfiguration.
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(2002)Journal ArticleWe have established a simulation model for phosphorus-doped silicon emitters using Fermi–Dirac statistics. Our model is based on a set of independently measured material parameters and on quantum mechanical calculations. In contrast to commonly applied models, which use Boltzmann statistics and apparent band-gap narrowing data, we use Fermi–Dirac statistics and theoretically derived band shifts, and therefore we account for the degeneracy effects on a physically sounder basis. This leads to unprecedented consistency and precision even at very high dopant densities. We also derive the hole surface recombination velocity parameter Spo by applying our model to a broad range of measurements of the emitter saturation current density. Despite small differences in oxide quality among various laboratories, Spo generally increases for all of them in a very similar manner at high surface doping densities Nsurf. Pyramidal texturing generally increases Spo by a factor of five. The frequently used forming gas anneal lowers Spo mainly in low-doped emitters, while an aluminum anneal (Al deposit followed by a heat cycle) lowers Spo at all Nsurf.
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(2002)Journal ArticleWe assess a broad range of published experiments to show that the density of states (DOS) at high-energy grain boundaries in silicon is appropriately described by the defect-pool model. This implies that the DOS of such grain boundaries depends strongly on the dopant density and on the position of the Fermi level during device processing. However, since high-energy grain boundaries consist of an amorphous layer that is confined to a width of a few angstroms, the DOS is "frozen in" after material processing and does not suffer the strong degradation effects commonly observed in bulk a-Si:H. By combining three-dimensional device modeling and the defect-pool model, we reproduce various test structures and polycrystalline thin-film Si solar cells considerably more precisely than in the past. Our simulation model potentially provides a link between processing conditions and grain boundary quality.