Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs

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Abstract
Current FPGA design flows do not readily support high-level, behavioural design or the use of run-time reconfiguration. Designers are thus discouraged from taking a high-level view of their systems and cannot fully exploit the benefits of programmable hardware. This paper reports on our advances towards the development of design technology that supports behavioural specification and compilation of FPGA designs and automatically manages FPGA chip virtualization.
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Author(s)
Diessel, Oliver
Malik, Usama
So, Keith
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Publication Year
2002
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Conference Paper
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UNSW Faculty
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download ep02diessel_0200405500.pdf 69.71 KB Adobe Portable Document Format
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