An FPGA Interpreter with Virtual Hardware Management

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Abstract
This paper describes the design of an interpreter that overcomes FPGA resource limitations for a class of control-oriented circuits by automatically partitioning, elaborating, and loading circuit components as directed by their execution. By providing a virtual hardware management facility, this enables us to implement large systems, specified in Circal, on small FPGA chips.
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Author(s)
Diessel, Oliver
Malik, Usama
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Publication Year
2002
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Conference Paper
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UNSW Faculty
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