Memory Data Protection for Single-Processor Based Embedded Systems

Abstract

Embedded systems are ubiquitous and widely used in a large spectrum of applications. Sensitive and security critical information is stored and processed in embedded devices, which has drawn attacks from various directions. The extent of damages from attacks is appalling.

Although software attacks, which have hitherto manifested themselves in the context of general-purpose computers, represent threats to embedded systems, an emerging class of physical attacks that particularly exploit the available physical-accesses offered by the embedded system, are becoming increasingly threatening.

Most of embedded systems are processor based with external memory components. The external memory is extremely vulnerable to physical attacks. Therefore, the confidentiality and integrity of the external memory are critical to the embedded systems security.

Existing cryptographic techniques, such as encryption, authentication algorithms, are employed for protecting the confidentiality and integrity of the memory data. Many security designs based on cryptographic primitives have been proposed. However, many have high processing and resource overhead, making them infeasible for embedded systems.

This thesis tackles the overhead issues of the security design in embedded systems. Specifically, it targets the security design for embedded systems that have the tamper-resistant processor and insecure off-chip memory, and it aims for offering the maximal security for the external memory protection while with the minimal on-chip resource cost and off-chip memory consumption.

We proposed a novel dynamic encryption key design that incurs small overhead in on-chip area, memory and power consumption, an innovative tag generation scheme that is both on-chip cost and off-chip memory efficient. Based on the proposed designs, we developed an effective memory data protection scheme that can highly resistant to physical attacks on the external memory and its buses while with low on-chip cost, memory consumption, and small impact on the overall performance. Evaluation platform has been developed to examine the design approaches proposed in the thesis. The experiment results demonstrate the effectiveness of our design approaches compared to the state-of-the-art designs.