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Abstract
In this Masters thesis a low power high speed 10 bit current steering D/A converter is designed for the efficient triggering of the quantum bits (qubits) which perform the quantum gate operations in a silicon quantum computer. These computers use the principle of quantum mechanical phenomena such as superposition and entanglement to perform quantum logics based on wide spread and matured Si technologies. Like digital computers characterized by classical bits 1 and 0, quantum computers also process information through qubits. The arrays of qubit, located in a quantum processor, must operate in deep cryogenic temperature and these qubits also need very fast pulse based classical control circuitry for the initialization, control and readout of their states. A low power 10 bit D/A converter operating in GHz range and at or below 4.2K and driving a 50Ω load can serve this purpose.
We have chosen a partially segmented current steering structure for the D/A converter designing as it has inherent direct driving capability of a resistive load and can provide the fastest response than its counterparts. In this converter, six most significant bits are thermometer coded and four least significant bits (LSBs) are binary weighted. Dual 1.5V power supply and complementary source and sink structure are used to ensure the lowest power dissipation. To compensate the mismatch effects (pronounced at 4.2K) of the current sources of the converter and to confirm that there are no missing analog output values (like missing code in an A/D converter), we have used source degenerated transistors, utilized an analog memory based calibration method and extended the full calibration procedure to the LSBs. A novel charge injection reduction technique is incorporated in the calibration procedure that allows the analog memory to balance the nonlinearity problem caused by charge injection.
To implement this converter in the low temperature, CMOS Silicon-on-Sapphire (SOS) process is our primary choice due to its high inherent unity gain frequency, fast switching speed and absence of kink effect and less parasitic capacitive effect on circuits. The complete system is designed in CADENCE using a fully depleted standard 0.5µm CMOS SOS process.