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Abstract
The aim of this thesis is to develop a hardware support which enables faster run-time partial reconfigurations for reconfigurable systems. The current configuration routing architecture of the reconfigurable systems imposes considerable amount of overheads by loading more configuration data than required onto the configuration memory. The overheads can be as costly as contributing up to 98.5% of the configuration latency. This leads to one of the major shortcomings in current FPGA technologies. Therefore, in order to increase the efficiency of run-time reconfiguration systems, it is crucial to reduce the reconfiguration overhead by reducing the lengths of the reconfiguration bitstreams. In this thesis, the reconfiguration bitstreams are minimized by two techniques: the concept of partial reconfigurations and the reduced reconfiguration granularities.
The proposed configuration routing system provides efficient access to non-contiguous reconfigurable locations in reconfigurable systems. It reduces the amount of configuration data in a partial reconfiguration bitstream by removing all the addressing information and pad zeroes which are present in Virtex-4 partial bitstreams. The system allows variable frame set sizes as well as variable reconfiguration granularities, thereby providing sufficient scalability and flexibility. The proposed system is readily applicable to SRAM-based FPGAs. The major advantage of the proposed system over the Virtex-4 architecture is the ability to reduce the configuration data significantly without additional addressing information when the reconfiguration granularities are small. The experimental results and simulations show that a proposed system with its hardware cost less than 50% of the Virtex-4 configuration routing architecture achieves speedups of up to 14.84% over the Virtex-4 devices when the reconfiguration granularity equals to a Virtex-4 frame. Moreover, the speedups increase up to 17.33% when the granularity is set to half of a Virtex-4 frame, and up to 56.51% when the granularity is set to a quarter of a Virtex-4 frame while maintaining the same hardware cost.