Digital Harmonic-Cancelling Sinusoidal Signal Synthesis

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Copyright: Aluthwala, Pasindu
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Abstract
Sinusoidal signal synthesizers are essential modules in a variety of electronic applications, such as communication systems, calibration and verification of analog/mixed-signal integrated circuits (ICs), and lab-on-chip medical/material analyzers. For several decades, researchers have worked on developing different types of sine-wave synthesizers. However, improving the balance between spectral purity, area cost, power consumption, and programmability of sine-wave synthesizers remains an intriguing research problem. The subject of this thesis is digital harmonic-cancelling sine-wave synthesizers (DHSSs). The first publication of a DHSS was in 1969. However, due to the overshadowing popularity of direct digital frequency synthesizers (DDFSs), the development of DHSSs had been stalled until a revival in recent years. DHSSs offer a better compromise between spectral purity, and area and power costs, compared to DDFSs. On the other hand, DHSSs lag behind DDFSs in terms of programmability. We envisage a future in which DHSSs replace DDFSs in applications where area and power cost efficiency is the primary requirement. With this vision in mind, we have worked in this research towards improving the programmability as well as the area and power cost effectiveness of DHSSs. In doing so, this research has resulted in three main contributions to the DHSS technology. The first contribution is a DHSS hardware architecture, which supports phase programmability. Phase programmability opens the door for DHSSs to be used in phase-shift keying (PSK) communication applications. The second contribution is a method of designing DHSSs, such that the resulting DHSSs break the 6 dB/bit rule. The 6 dB/bit rule governs the compromise between spectral purity, and area and power costs in DDFSs. Furthermore, previous DHSS related work have not explored the design space of DHSSs enough to realize that DHSSs could break the 6 dB/bit rule. The third contribution is a dynamic element matching (DEM) technique to reduce the effect of mismatch while preserving the area and power cost efficiency of DHSSs. The theoretical proposals made in this thesis have been verified by implementing and testing two DHSS IC prototypes. One prototype was designed to be phase programmable, and it has been used to demonstrate the usability of DHSSs as PSK modulators. The other prototype utilized the proposed DEM technique. Activating DEM improved the figure of merit of the DHSS by 40 %, compared to the same DHSS with DEM deactivated. Both DHSS prototypes used the design method presented in this thesis, and they have broken the 6 dB/bit rule by performing at 8 dB/bit and 10 dB/bit.
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Author(s)
Aluthwala, Pasindu
Supervisor(s)
Parameswaran, Sri
Lehmann, Torsten
Neil, Weste
Andrew, Adams
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Publication Year
2017
Resource Type
Thesis
Degree Type
PhD Doctorate
UNSW Faculty
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