Study of the design of 28 nm complementary metal-oxide semiconductor dual mode digital low voltage drop out regulator

Abstract

In this paper we will demonstrate the implementation of a low-dropout hybrid regulator (LDO) in a 28 nm TSMC CMOS technology process that comprise a continuous to discrete time feedback loop. The proposed LDO will be given an apriori signal to signal between low and high load current states. This mixed mode design is scalable ensuring best regulation at different load currents for a dual or multi-channel LDO designs. The maximum undershoot is found to be under 20 mV and steady state ripple less than 15 mV. The rise time was found by simulation to be under 0.02 $\mu$s with the potential to be even faster as the state of each current channel is stored. The sampling time is 100 MHz and reference voltage is 850 mV with input voltage of 900 mV.

Research will be made into the design and behaviour of a hybrid digital analog low dropout out voltage regulator for a Serialization/Deserialization ("SerDes") application that requires the supply of 1 mA with 40 mA pulses for 2 ns at up to 100 MHz with a 50 ps current rise/fall time. The voltage output must be stable within 20 mV. This excludes 500 ps during the current change. The input current will be constant. The LDO will comprise a digital control loop.