Sigma-delta modulation circuits with digital assistance

Abstract

CMOS technology scaling has enabled sustained performance improvements of electronic circuits through faster, highly integrated, and more energy efficient digital circuits. In advanced nanometer CMOS processes, however, analogue circuit implementation faces challenges that limits its performance. Analogue-to-digital and digital-to-analogue converters are important parts of most electronic systems, and circuit innovation is required to maintain their performance improvement trend. Sigma-delta modulation is an attractive technique for this purpose due to its ability to perform in the presence of analogue circuit imperfection.

This thesis proposes simple analogue structures with digital assistance implemented within sigma-delta modulation circuits for compatibility with nanoscale CMOS processes. For this purpose, we consider two aspects of sigma-delta modulation circuits. Firstly, we implement a multi-bit digital-to-analogue converter (DAC) in a sigma-delta modulation (SDM) DAC that is suitable for CMOS scaling. A shunt-shunt resistive voltage divider DAC is proposed for this purpose, consisting of an array of uniform resistors and inverter switches for use in a multi-stage SDM DAC with dynamic element matching. Chip measurement results of the resistive DAC in CMOS 180 nm process show that our approach is suitable for nanoscale CMOS scaling with its rail-to-rail output swing. Furthermore, the DAC features a code-independent output impedance for improved static linearity, where dynamic nonlinearity becomes the limiting performance factor. Classical current-steering DAC was studied for comparison purpose.

The second aspect of this thesis focuses on the use of an inverter-based positive-feedback operational transconductance amplifier (OTA) with digital configurability for continuous-time sigma-delta modulator (CT-SDM) circuits. This OTA requires tuning for its intended operation, and we propose a digital-intensive tuning technique that incorporates elements from the CT-SDM circuit. We present a design example of a second-order CT-SDM circuit in CMOS 65 nm process with simulated results showing the potential of our approach. We investigate the subthreshold operation of the digitally-configurable OTA in a first-order sigma-delta modulator, and present experimental results using a digitally-configurable OTA chip in CMOS 180 nm showing its feasibility in low voltage environment. Experimental results validate the effectiveness of our proposed digital OTA tuning technique which enables the practical use of digitally-configurable positive-feedback OTAs in CT-SDM circuits.