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Abstract
The performance of a computing system heavily depends on the memory hierarchy. Fast but expensive cache memories are commonly employed to bridge the increasing performance gap between processors and memory devices. Benefits drawn from a cache vary significantly with the diverse memory access patterns of software application programs, especially in the domain of embedded systems. Modern embedded processors acknowledge this relation between applications and caches, by incorporating cache memories which are configurable at design-time.
Design space exploration of caches in an application specific system is a difficult problem, which typically takes days to solve, if not weeks, using software-based techniques. The problem becomes more complex for multiprocessor systems with hierarchical caches, executing many application programs. A typical such design space can be of vast proportions containing up to several trillions of unique design points, which is infeasible to be accurately explored using existing techniques.
This dissertation presents a design space exploration framework which uses hardware accelerated simulation to quickly determine the best set of cache configurations for a multiprocessor cache hierarchy. The proposed framework was able to achieve up to 456 times faster simulation times compared to the fastest known software-based simulator. Further, a novel exploration algorithm is presented, which was able to improve the cache access times by up to 18.9%, while reducing total cache size by up to 74.15% at the same time.
A new run-time concept is introduced, called switchable cache, where a processor can select from multiple pre-defined cache configurations, leveraging the abundant transistors available due to what is known as the dark silicon phenomenon. An architecture to enable seamless integration of multiple cache configurations is described. A novel design space exploration algorithm is presented to rapidly pre-determine the optimal set of configurations at design-time, for a given group of applications. The use of Answer Set Programming, which guarantees optimal solutions for NP-Hard problems, is explored to reliably solve the switchable cache tuning problem.