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Abstract
MultiProcessor System on Chip (MPSoC) architecture has been widely researched for the implementation of video coding applications due to its ability to process data in parallel, its flexibility, high performance, and low cost. However, in recent times, with the release of more complex video coding standards as well as the requirement to transfer high quality video signals through broadband networks in real-time and shorter time-to-market, system designers have been facing many challenges when developing such complicated multiprocessor systems.
This thesis introduces a platform for a H.264/Advanced Video Coding (AVC) encoder which is both flexible (allows software upgrades) and scalable (supports multiple resolutions), and supports high video quality (by using both intra prediction and inter prediction) and allows high throughput (by exploiting slice-level/Group of Macroblocks-level and pixel-level/Intra Macroblock-level parallelisms). Our platform uses multiple Application Specific Instruction set Processors (ASIPs) with local and shared memories, and hardware accelerators (in the form of custom instructions). Our platform can be configured to use a particular number of ASIPs (slices/Group of Macroblocks per video frame) for a specific video resolution at design-time. The MPSoC architecture is automatically generated by our platform and the H.264 software does not need any modification, which enables quick design space exploration. We implemented the proposed platform in a commercial design environment, and illustrated its utility by creating systems with up to 170 ASIPs supporting resolutions up to Full High Definition (HD1080). We further showed how power gating can be used in our platform to save on energy consumption. We also present a multi-ASIP architecture to provide for, and evaluate the performance of, a flexible and scalable platform for motion estimation at the HD1080 resolution, which uses hand-coded and automatically generated hardware accelerators separately.
It took many months to design and introduce hardware-software co-design platforms. Based on our methods and results, future designers will only need to spend a few minutes in design space to modify text-based configurations, to achieve expectedly optimized systems without changing any source code.