Download files
Abstract
The current state-of-the-art power saving designs progressively evolve, boosted by the notable advancements in microelectronics technologies. However, due to scaling in size of the electrodes in the modern biomedical implants, high-voltage power supplies (some 5-20V) are necessitated for electrodes actuation purposes while most the implantable electronic sub-systems are operating under low-voltage power supplies (3V) generated by linear regulators with degenerated power efficiency. Therefore, on system point of view, modern techniques on power saving fall far behind the system level requirements and will have reliability issues in the specific applications such as biomedical implants.
The major challenge in our research presented in this thesis is the design of linear power supplies with current recycling capabilities and is required to cope with high-voltage stimulus power supply. For an implantable device, the linear power supply circuit is characterised to have low power dissipation, small real-estate and reliable as well as stable operation under wide range of power supply voltages.
In this thesis, we propose a current recycling technique in linear regulators for biomedical implants. The unique technology allows linear regulators being stacked, dividing the high-voltage power supply domain into several low-voltage supply domains; current can be recycled between these power supplies by having a current recycling node and power efficiency in the low-voltage powered circuits can be enhanced. Linear regulators are designed such that they both have series and shunt regulation capabilities. A dual-stacked current recycling linear power supply has been implemented in 0.35um high-voltage CMOS process with fully considerations of process variations and mismatch. The fabricated linear power supply circuit occupies an active silicon area of 0.45mm2, achieving maximum Power Saving Factor and Current Efficiency of 48.6% and 97.2%, respectively, with quiescent current of only 45uA. Furthermore, with our current recycling technology, a dual-stacked topology can be easily extended to a multiple-stacked structure. A triple-stacked current recycling linear power supply has been implemented using 0.35um high-voltage CMOS process, achieving maximum Power Saving Factor and Current Efficiency of 65.5% and 96.4%, respectively.