Download files
Abstract
Over the past decades, the electrical and functional performances of neuro-stimulators (stimulators) have been shown to successfully restore impaired function to individuals, such as a cochlea implant for the deaf and vision prosthesis for the blind. Along with this success, ensuring safe operation of stimulators for a long term period is one of the major concerns.
Safety, in terms of stimulators' electrical performances, can be related mainly to two factors; the zero-net charge transfer (perfect charge balance) to tissue and the heat generated by power dissipation at a stimulating tissue and by electronics.
Therefore, for a safe neural stimulation, stimulators are required to maintain perfect charge balance and minimize power consumption during neural stimulation.
This thesis presents the development of the implantable stimulating circuitry (using HV CMOS process), which includes a stimulator and a high gain current mirror amplifier.
The emphasis was given to develop a stimulator, featured in precise charge balancing capability and low power consumption, for vision prosthesis, specifically, a retinal implant.
Employing a dynamic current mirror at the output of a stimulator achieves precise charge balance without dedicating large area, as the charge imbalance in current mode stimulation is mainly contributed by the effect of CMOS process variation and mismatch on the current source and sink drivers at the output of a stimulator.
With this scheme, charge imbalance of less than 100pC was measured, when delivering 100nC to the tissue with a full scale current of approximately 1mA. This is equivalent to less than 0.1% error, sufficient to ensure safety during stimulation.
Low power consumption was achieved in a number of ways, such as usage of small bias current, sharing of key biasing blocks, and utilising a short duty cycle for stimulation. Less than 50uW was consumed during stand-by mode, mostly by bias circuitry.
A high gain current mirror amplifier, in the appendix, was proposed and simulated for biomedical circuits, achieving small area, low power consumption, and fast settling time.
Apart from these, a novel technique to reduce the variation of CMOS integrated resistor's value was proposed. To validate this technique, a resistor based 5 bit DAC, forming a part of the stimulator, was fabricated. The measurement result indicated that the variation of CMOS integrated resistors is reduced by 33% and the DAC shows a monotonic characteristic.