Publication:
Dynamic scheduling of tasks on partially reconfigurable FPGAs
Dynamic scheduling of tasks on partially reconfigurable FPGAs
dc.contributor.author | Diessel, Oliver | en_US |
dc.contributor.author | ElGindy, Hossam | en_US |
dc.contributor.author | Middendorf, M | en_US |
dc.contributor.author | Schmeck, H | en_US |
dc.contributor.author | Schmidt, B | en_US |
dc.date.accessioned | 2021-11-25T13:26:47Z | |
dc.date.available | 2021-11-25T13:26:47Z | |
dc.date.issued | 2000 | en_US |
dc.description.abstract | Field-programmable gate arrays (FPGAs) which allow partial reconfiguration at run time can be shared among multiple independent tasks. When the sequence of tasks to be performed is unpredictable, the FPGA controller needs to make allocation decisions online. Since online allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit noncontiguous, resources available to service them. The time to complete tasks is consequently longer and the utilisation of the FPGA is lower than it could be. It is proposed that a subset of the tasks executing on the FPGA be rearranged when to do so allows the next pending task to be processed sooner. Methods are described and evaluated for overcoming the NP-hard problems of identifying feasible rearrangements and scheduling the rearrangements when moving tasks are reloaded from off-chip. | en_US |
dc.identifier.issn | 1350-2387 | en_US |
dc.identifier.uri | http://hdl.handle.net/1959.4/39656 | |
dc.language | English | |
dc.language.iso | EN | en_US |
dc.rights | CC BY-NC-ND 3.0 | en_US |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
dc.source | Legacy MARC | en_US |
dc.title | Dynamic scheduling of tasks on partially reconfigurable FPGAs | en_US |
dc.type | Journal Article | en |
dcterms.accessRights | open access | |
dspace.entity.type | Publication | en_US |
unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
unsw.description.publisherStatement | ©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
unsw.identifier.doiPublisher | http://dx.doi.org/10.1049/ip-cdt:20000485 | en_US |
unsw.relation.faculty | Engineering | |
unsw.relation.ispartofissue | 3 | en_US |
unsw.relation.ispartofjournal | IEE Proceedings - Computers and Digital Techniques | en_US |
unsw.relation.ispartofpagefrompageto | 181-188 | en_US |
unsw.relation.ispartofvolume | 147 | en_US |
unsw.relation.originalPublicationAffiliation | Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | ElGindy, Hossam, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Middendorf, M | en_US |
unsw.relation.originalPublicationAffiliation | Schmeck, H | en_US |
unsw.relation.originalPublicationAffiliation | Schmidt, B | en_US |
unsw.relation.school | School of Computer Science and Engineering | * |
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