Publication:
A configuration memory architecture for fast run-time reconfiguration of FPGAs
A configuration memory architecture for fast run-time reconfiguration of FPGAs
dc.contributor.author | Malik, Usama | en_US |
dc.contributor.author | Diessel, Oliver | en_US |
dc.date.accessioned | 2021-11-25T13:27:00Z | |
dc.date.available | 2021-11-25T13:27:00Z | |
dc.date.issued | 2005 | en_US |
dc.description.abstract | This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial reconfiguration that allows significant configuration re-use while switching from one circuit to another. The proposed configuration memory works by reading on-chip configuration data into a buffer, modifying them based on the externally supplied data and writing them back to their original registers. A prototype implementation of the proposed design in a 90nm cell library indicates that the new memory adds less than 1% area to a commercially available FPGA implemented using the same library. The proposed design reduces the reconfiguration time for a wide set of benchmark circuits by 63%. However, power consumption during reconfiguration increases by a factor of 2.5 because the read-modify-write strategy results in more switching in the memory array. | en_US |
dc.identifier.isbn | 0780393627 | en_US |
dc.identifier.uri | http://hdl.handle.net/1959.4/39666 | |
dc.language | English | |
dc.language.iso | EN | en_US |
dc.publisher | IEEE | en_US |
dc.rights | CC BY-NC-ND 3.0 | en_US |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
dc.source | Legacy MARC | en_US |
dc.subject.other | FPGAs | en_US |
dc.subject.other | Memory architecture | en_US |
dc.title | A configuration memory architecture for fast run-time reconfiguration of FPGAs | en_US |
dc.type | Conference Paper | en |
dcterms.accessRights | open access | |
dspace.entity.type | Publication | en_US |
unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
unsw.description.publisherStatement | ©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
unsw.identifier.doiPublisher | http://dx.doi.org/10.1109/FPL.2005.1515802 | en_US |
unsw.publisher.place | Finland | en_US |
unsw.relation.faculty | Engineering | |
unsw.relation.ispartofconferenceLocation | Finland | en_US |
unsw.relation.ispartofconferenceName | 2005 International conference on field programmable logic (FPL 2005) | en_US |
unsw.relation.ispartofconferenceProceedingsTitle | FPL 2005: International conference on field programmable logic | en_US |
unsw.relation.ispartofconferenceYear | 2005 | en_US |
unsw.relation.ispartofpagefrompageto | 636-639 | en_US |
unsw.relation.originalPublicationAffiliation | Malik, Usama, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.school | School of Computer Science and Engineering | * |
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