A configuration system architecture supporting bit-stream compression for FPGAs

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Abstract
This paper presents an investigation and design of an enhanced on-chip configuration memory system that can reduce the time to (re)configure an FPGA. The proposed system accepts configuration data in a compressed form and performs decompression internally, The resulting FPCA can be (re)configured in time proportional to the size of the compressed bit-stream. The compression technique exploits the redundancy present in typical configuration data. An analysis of configurations corresponding to a set of benchmark circuits reveals that data that controls the same types of configurable elements have a common byte that occurs at a significantly higher frequency. This common byte is simply broadcast to all instances of that element. This step is followed by byte updates if required. The new configuration system has modest hardware requirements and was observed to reduce reconfiguration time for the benchmark set by two-thirds on average.
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Author(s)
Della Torre, Marco
Malik, Usama
Diessel, Oliver
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Publication Year
2005
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Conference Paper
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UNSW Faculty
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download acsac05dellatorre.pdf 231.19 KB Adobe Portable Document Format
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