Publication:
Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs
Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs
| dc.contributor.author | Diessel, Oliver | en_US |
| dc.contributor.author | Malik, Usama | en_US |
| dc.contributor.author | So, Keith | en_US |
| dc.date.accessioned | 2021-11-25T13:27:05Z | |
| dc.date.available | 2021-11-25T13:27:05Z | |
| dc.date.issued | 2002 | en_US |
| dc.description.abstract | Current FPGA design flows do not readily support high-level, behavioural design or the use of run-time reconfiguration. Designers are thus discouraged from taking a high-level view of their systems and cannot fully exploit the benefits of programmable hardware. This paper reports on our advances towards the development of design technology that supports behavioural specification and compilation of FPGA designs and automatically manages FPGA chip virtualization. | en_US |
| dc.identifier.isbn | 9783540440499 | en_US |
| dc.identifier.issn | 0302-9743 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1959.4/39665 | |
| dc.language | English | |
| dc.language.iso | EN | en_US |
| dc.publisher | Springer Berlin / Heidelberg | en_US |
| dc.rights | CC BY-NC-ND 3.0 | en_US |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
| dc.source | Legacy MARC | en_US |
| dc.title | Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs | en_US |
| dc.type | Conference Paper | en |
| dcterms.accessRights | open access | |
| dspace.entity.type | Publication | en_US |
| unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
| unsw.description.publisherStatement | The original publication is available at www.springerlink.com | en_US |
| unsw.identifier.doiPublisher | http://dx.doi.org/10.1007/3-540-45706-2_41 | en_US |
| unsw.relation.faculty | Engineering | |
| unsw.relation.ispartofconferenceLocation | Paderborn, Germany | en_US |
| unsw.relation.ispartofconferenceName | Euro-Par 2002: 8th International Euro-Par Conference | en_US |
| unsw.relation.ispartofconferenceProceedingsTitle | Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs: Lecture Notes in Artificial Intelligence, Volume 2400 | en_US |
| unsw.relation.ispartofconferenceYear | 2002 | en_US |
| unsw.relation.ispartofpagefrompageto | 314-317 | en_US |
| unsw.relation.originalPublicationAffiliation | Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.originalPublicationAffiliation | Malik, Usama, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.originalPublicationAffiliation | So, Keith, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.school | School of Computer Science and Engineering | * |
Files
Original bundle
1 - 1 of 1