Electron Tunnelling in Atomically Precise 3D Silicon Nanostructures

Abstract

In this thesis we investigate quantum tunnelling of electrons in nanoscale tunnel junctions made from STM-patterned highly phosphorus doped silicon monolayers. Whilst the devices are monolayer doped, they are encapsulated in epitaxial silicon to form atomically abrupt 3D crystalline junctions that have multiple use cases in the manipulation of spin states in silicon for quantum information.

First we investigate how to control the tunnelling resistance in these simple junctions by precision engineering of the junction length with STM lithography. By patterning the hydrogen resist with the tunnel junction edges along a dimer row in the [-110] crystalline direction we achieved a lithography accuracy of ±0.38nm. This precision patterning allowed us to increase the reproducibility of tunnel junction resistances to within 5% and demonstrate the exponential scaling of tunnelling resistance with junction length L.

Second we investigated the tunnelling resistance as a function of lead width. By precision patterning the hydrogen resist along the dimer row in the [110] crystalline direction we reduced the lithographic accuracy of the junction length to ±0.77nm but increased the accuracy of the lead width to ±0.38nm. We observed a four order of magnitude change in the resistance of a 15nm long junction as the lead width changed from 7 to 15nm. To understand this variability, we conducted atomistic NEMO calculations and showed that the density of the states in these heavily phosphorus doped silicon wires is very sensitive to lead width. For thinner leads, where the width, W is <7nm the variability in the density of states is 0.7x108 meV-1 compared to 3.0x108 meV-1 at W~15nm. By plotting the resistances of all junctions as a function of lead width we observed an unexpected four order-of-magnitude change in the tunnelling resistance at W∼10 nm. Whilst this this could not be understood using current modelling, we speculate that it is related to size effects of the junction where the width of the leads matches the electron mean free path.

We developed two unique atomic precision patterning techniques to realise 3D epitaxial gating. The first used kinetic growth manipulation to reduce the thermal budget during growth to minimise phosphorus diffusion to 0.66nm whilst achieving surfaces with 20nm2 island sizes, suitable for precision STM lithography. The second was to use the topographic height differential of the surface between STM-patterned doped surfaces and those with no underlying phosphorus atoms. Here despite ~100nm epitaxial silicon growth it was possible to observe a 0.4nm height differential. Using these two new techniques we were able to pattern 30nm wide vertically separated 3D epitaxial gates directly above tunnel junctions of size 9nm(W) x 17nm (L) and 9nm(W) x 30nm (L) with ±5nm accuracy. For the short junction we demonstrated strong capacitive coupling (a~0.36) – three times higher than for in-plane gates and showed we could tune the tunnel junction from 0.1 MOhm to 3.1 MOhm changing the barrier height from ∼0meV to 186 meV. Since the gate was more than three times narrower than previous 3D epitaxial gates, we were able to integrate two independent gates above two tunnel junctions in series within a single device. Using this device we demonstrated classical logic with an on/off ratio of ∼1000-2000.

Finally we investigated the control of single electron tunnelling between a donor quantum dot qubit and an electron reservoir using a 3D epitaxial gate. We demonstrated that the tunnel rate Γ of electrons between the qubit and reservoir can be tuned from 5Hz to 10kHz which is notable since in-plane gates have not been shown to date to tune tunnel rates. This therefore represents a new capability in Si:P quantum computing devices. We discuss how future optimisation of device design will allow control of electron tunnelling for high fidelity qubit readout and controllable exchange coupling.