Publication:
The enotropy of FPGA reconfiguration
The enotropy of FPGA reconfiguration
dc.contributor.author | Malik, Usama | en_US |
dc.contributor.author | Diessel, Oliver | en_US |
dc.date.accessioned | 2021-11-25T13:26:55Z | |
dc.date.available | 2021-11-25T13:26:55Z | |
dc.date.issued | 2006 | en_US |
dc.description.abstract | In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple off-the-shelf compression techniques such as Golomb encoding and hierarchical vector compression achieve compression results that are within 1-10% of the theoretical bound. We present an enhanced configuration memory system based on the hierarchical vector compression technique that accelerates reconfiguration in proportion to the amount of compression achieved. The proposed system demands little additional chip area and can be clocked at the same rate as the Virtex configuration clock. | en_US |
dc.identifier.uri | http://hdl.handle.net/1959.4/39658 | |
dc.language | English | |
dc.language.iso | EN | en_US |
dc.publisher | Publidisa | en_US |
dc.rights | CC BY-NC-ND 3.0 | en_US |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
dc.source | Legacy MARC | en_US |
dc.title | The enotropy of FPGA reconfiguration | en_US |
dc.type | Conference Paper | en |
dcterms.accessRights | open access | |
dspace.entity.type | Publication | en_US |
unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
unsw.description.publisherStatement | ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
unsw.identifier.doiPublisher | http://dx.doi.org/10.1109/FPL.2006.311223 | en_US |
unsw.publisher.place | Spain | en_US |
unsw.relation.faculty | Engineering | |
unsw.relation.ispartofconferenceLocation | Madrid, Spain | en_US |
unsw.relation.ispartofconferenceName | International conference on field programmable logic and applications | en_US |
unsw.relation.ispartofconferenceProceedingsTitle | International conference on field programmable logic and applications, Proceedings | en_US |
unsw.relation.ispartofconferenceYear | 2006 | en_US |
unsw.relation.ispartofpagefrompageto | 261-266 | en_US |
unsw.relation.originalPublicationAffiliation | Malik, Usama, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.school | School of Computer Science and Engineering | * |
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