The enotropy of FPGA reconfiguration Malik, Usama en_US Diessel, Oliver en_US 2021-11-25T13:26:55Z 2021-11-25T13:26:55Z 2006 en_US
dc.description.abstract In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple off-the-shelf compression techniques such as Golomb encoding and hierarchical vector compression achieve compression results that are within 1-10% of the theoretical bound. We present an enhanced configuration memory system based on the hierarchical vector compression technique that accelerates reconfiguration in proportion to the amount of compression achieved. The proposed system demands little additional chip area and can be clocked at the same rate as the Virtex configuration clock. en_US
dc.language English
dc.language.iso EN en_US
dc.publisher Publidisa en_US
dc.rights CC BY-NC-ND 3.0 en_US
dc.rights.uri en_US
dc.source Legacy MARC en_US
dc.title The enotropy of FPGA reconfiguration en_US
dc.type Conference Paper en
dcterms.accessRights open access
dspace.entity.type Publication en_US
unsw.description.publisherStatement ©2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. en_US
unsw.identifier.doiPublisher en_US Spain en_US
unsw.relation.faculty Engineering
unsw.relation.ispartofconferenceLocation Madrid, Spain en_US
unsw.relation.ispartofconferenceName International conference on field programmable logic and applications en_US
unsw.relation.ispartofconferenceProceedingsTitle International conference on field programmable logic and applications, Proceedings en_US
unsw.relation.ispartofconferenceYear 2006 en_US
unsw.relation.ispartofpagefrompageto 261-266 en_US
unsw.relation.originalPublicationAffiliation Malik, Usama, Computer Science & Engineering, Faculty of Engineering, UNSW en_US
unsw.relation.originalPublicationAffiliation Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW en_US School of Computer Science and Engineering *
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