Publication:
Fast Address-Space Switching on the StrongARM SA-1100 Processor
Fast Address-Space Switching on the StrongARM SA-1100 Processor
dc.contributor.author | Wiggins, A | en_US |
dc.contributor.author | Heiser, Gernot | en_US |
dc.date.accessioned | 2021-11-25T13:32:47Z | |
dc.date.available | 2021-11-25T13:32:47Z | |
dc.date.issued | 2000 | en_US |
dc.description.abstract | The StrongARM SA-1100 is a high-speed low-power processor aimed at embedded and portable applications. Its architecture features virtual caches and TLBs which are not tagged by an address-space identifier. Consequently, context switches on that processor are potentially very expensive, as they may require complete flushes of TLBs and caches. This report presents the design of an address-space management technique for the StrongARM which minimises TLB and cache flushes and thus context switching costs. The basic idea is to implement the top-level of the (hardware-walked) page-table as a cache for page directory entries for different address spaces. This allows switching address spaces with minimal overhead as long as the working sets do not overlap. For small (<=32MB) address spaces further improvements are possible by making use of the StrongARM`s re-mapping facility. Our technique is discussed in the context of the L4 microkernel in which it will be implemented. | en_US |
dc.identifier.isbn | 769505120 | en_US |
dc.identifier.uri | http://hdl.handle.net/1959.4/39927 | |
dc.language | English | |
dc.language.iso | EN | en_US |
dc.publisher | IEEE Computer Society | en_US |
dc.rights | CC BY-NC-ND 3.0 | en_US |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
dc.source | Legacy MARC | en_US |
dc.title | Fast Address-Space Switching on the StrongARM SA-1100 Processor | en_US |
dc.type | Conference Paper | en |
dcterms.accessRights | open access | |
dspace.entity.type | Publication | en_US |
unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
unsw.description.publisherStatement | ©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
unsw.identifier.doiPublisher | http://dx.doi.org/10.1109/ACAC.2000.824330 | en_US |
unsw.publisher.place | Los Alamitos, CA, USA | en_US |
unsw.relation.faculty | Engineering | |
unsw.relation.ispartofconferenceLocation | Canberra, Australia | en_US |
unsw.relation.ispartofconferenceName | 5th Australasian Computer Architecture Conference | en_US |
unsw.relation.ispartofconferenceProceedingsTitle | Computer Architecture 2000 | en_US |
unsw.relation.ispartofconferenceYear | 2000 | en_US |
unsw.relation.ispartofpagefrompageto | 97-104 | en_US |
unsw.relation.originalPublicationAffiliation | Wiggins, A | en_US |
unsw.relation.originalPublicationAffiliation | Heiser, Gernot, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.school | School of Computer Science and Engineering | * |
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