Fast Address-Space Switching on the StrongARM SA-1100 Processor

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Abstract
The StrongARM SA-1100 is a high-speed low-power processor aimed at embedded and portable applications. Its architecture features virtual caches and TLBs which are not tagged by an address-space identifier. Consequently, context switches on that processor are potentially very expensive, as they may require complete flushes of TLBs and caches. This report presents the design of an address-space management technique for the StrongARM which minimises TLB and cache flushes and thus context switching costs. The basic idea is to implement the top-level of the (hardware-walked) page-table as a cache for page directory entries for different address spaces. This allows switching address spaces with minimal overhead as long as the working sets do not overlap. For small (<=32MB) address spaces further improvements are possible by making use of the StrongARM`s re-mapping facility. Our technique is discussed in the context of the L4 microkernel in which it will be implemented.
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Author(s)
Wiggins, A
Heiser, Gernot
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Publication Year
2000
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Conference Paper
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UNSW Faculty
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download acac-l4sa.pdf 62.58 KB Adobe Portable Document Format
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