Publication:
A novel instruction scratchpad memory optimization method based on concomitance metric

dc.contributor.author Janapsatya, Andhi en_US
dc.contributor.author Ignjatovic, Aleksandar en_US
dc.contributor.author Parameswaran, Sri en_US
dc.date.accessioned 2021-11-25T13:00:42Z
dc.date.available 2021-11-25T13:00:42Z
dc.date.issued 2006 en_US
dc.description.abstract Scratchpad memory has been introduced as a replacement for cache memory as it improves the performance of certain embedded systems. Additionally, it has also been demonstrated that scratchpad memory can significantly reduce the energy consumption of the memory hierarchy of embedded systems. This is significant, as the memory hierarchy consumes a substantial proportion of the total energy of an embedded system. This paper deals with optimization of the instruction memory scratchpad based on a novel methodology that uses a metric which we call the concomitance. This metric is used to find basic blocks which are executed frequently and in close proximity in time. Once such blocks are found, they are copied into the scratchpad memory at appropriate times; this is achieved using a special instruction inserted into the code at appropriate places. For a set of benchmarks taken from Mediabench, our scratchpad system consumed just 59% (avg) of the energy of the cache system, and 73% (avg) of the energy of the state of the art scratchpad system, while improving the overall performance. Compared to the state of the art method, the number of instructions copied into the scratchpad memory from the main memory is reduced by 88%. en_US
dc.description.uri http://www.aspdac.com/aspdac2006/cfd/ en_US
dc.identifier.isbn 0780394518 en_US
dc.identifier.uri http://hdl.handle.net/1959.4/38931
dc.language English
dc.language.iso EN en_US
dc.publisher IEEE en_US
dc.rights CC BY-NC-ND 3.0 en_US
dc.rights.uri https://creativecommons.org/licenses/by-nc-nd/3.0/au/ en_US
dc.source Legacy MARC en_US
dc.subject.other Scratchpad memory. en_US
dc.subject.other Cache memory. en_US
dc.subject.other Memory structures. en_US
dc.title A novel instruction scratchpad memory optimization method based on concomitance metric en_US
dc.type Conference Paper en
dcterms.accessRights open access
dspace.entity.type Publication en_US
unsw.accessRights.uri https://purl.org/coar/access_right/c_abf2
unsw.description.publisherStatement © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. en_US
unsw.identifier.doi https://doi.org/10.26190/unsworks/420
unsw.publisher.place USA en_US
unsw.relation.faculty Engineering
unsw.relation.ispartofconferenceLocation Yokohama, Japan en_US
unsw.relation.ispartofconferenceName 11th Asia and South Pacific Design Automation Conference en_US
unsw.relation.ispartofconferenceProceedingsTitle ASPDAC 2006, Proceedings en_US
unsw.relation.ispartofconferenceYear 2006 en_US
unsw.relation.ispartofpagefrompageto 612-617 en_US
unsw.relation.originalPublicationAffiliation Janapsatya, Andhi, Computer Science & Engineering, Faculty of Engineering, UNSW en_US
unsw.relation.originalPublicationAffiliation Ignjatovic, Aleksandar, Computer Science & Engineering, Faculty of Engineering, UNSW en_US
unsw.relation.originalPublicationAffiliation Parameswaran, Sri, Computer Science & Engineering, Faculty of Engineering, UNSW en_US
unsw.relation.school School of Computer Science and Engineering *
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
JanapsatyaNovel.pdf
Size:
302.8 KB
Format:
application/pdf
Description:
Resource type