Publication:
Module graph merging and placement to reduce reconfiguration overheads in paged FPGA devices
Module graph merging and placement to reduce reconfiguration overheads in paged FPGA devices
dc.contributor.author | Koh, Shannon | en_US |
dc.contributor.author | Diessel, Oliver | en_US |
dc.date.accessioned | 2021-11-25T13:26:50Z | |
dc.date.available | 2021-11-25T13:26:50Z | |
dc.date.issued | 2007 | en_US |
dc.description.abstract | Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel method to reduce reconfiguration time by maximising wire use and minimising wire reconfiguration. This builds upon our previously-presented methodology for creating modular, dynamically-reconfigurable applications targeted to an FPGA. The application of our techniques is demonstrated on an optical flow problem and show that graph merging can reduce reconfiguration delay by 50%. | en_US |
dc.identifier.isbn | 1424410606 | en_US |
dc.identifier.uri | http://hdl.handle.net/1959.4/39662 | |
dc.language | English | |
dc.language.iso | EN | en_US |
dc.publisher | IEEE | en_US |
dc.rights | CC BY-NC-ND 3.0 | en_US |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
dc.source | Legacy MARC | en_US |
dc.title | Module graph merging and placement to reduce reconfiguration overheads in paged FPGA devices | en_US |
dc.type | Conference Paper | en |
dcterms.accessRights | open access | |
dspace.entity.type | Publication | en_US |
unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
unsw.description.publisherStatement | ©2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
unsw.identifier.doiPublisher | http://dx.doi.org/10.1109/FPL.2007.4380662 | en_US |
unsw.publisher.place | TU Delft, The Netherlands | en_US |
unsw.relation.faculty | Engineering | |
unsw.relation.ispartofconferenceLocation | Amsterdam, Netherlands | en_US |
unsw.relation.ispartofconferenceName | International conference on field-programmable logic 2007 | en_US |
unsw.relation.ispartofconferenceProceedingsTitle | International conference on field-programmable logic 2007, Proceedings | en_US |
unsw.relation.ispartofconferenceYear | 2007 | en_US |
unsw.relation.ispartofpagefrompageto | 293-298 | en_US |
unsw.relation.originalPublicationAffiliation | Koh, Shannon, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.school | School of Computer Science and Engineering | * |
Files
Original bundle
1 - 1 of 1