Module graph merging and placement to reduce reconfiguration overheads in paged FPGA devices

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Abstract
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel method to reduce reconfiguration time by maximising wire use and minimising wire reconfiguration. This builds upon our previously-presented methodology for creating modular, dynamically-reconfigurable applications targeted to an FPGA. The application of our techniques is demonstrated on an optical flow problem and show that graph merging can reduce reconfiguration delay by 50%.
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Author(s)
Koh, Shannon
Diessel, Oliver
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Publication Year
2007
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Conference Paper
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UNSW Faculty
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download fpl07koh_0200704410.pdf 729.69 KB Adobe Portable Document Format
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