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Abstract
This thesis demonstrates the successful development of surface-gated, highly phosphorus doped single electron transistors, defined by scanning probe lithography and low-temperature silicon molecular beam epitaxy. In order to fabricate these devices, a custom ultra-high vacuum technique was developed to grow silicon dioxide as a gate dielectric at low temperatures to prevent thermal diffusion of the buried STM patterned dopants. This technique combined atomic oxygen generated using an RF plasma source with a coincident flux of sublimated silicon to grow silicon dioxide at temperatures down to 160 degrees C at growth rates of 0.3nm.min^−1. Using aluminium electrodes deposited on the dielectric, aligned to our buried STM-patterned dopants, we were able to form atomically-abrupt, surface-gated single electron transistors.
We performed chemical and structural analyses of the low temperature oxide using STM, TEM, XPS, and ellipsometry. These analyses indicated the oxide had low suboxide content and a sharp interface with the silicon substrate (< 1nm) comparable to high quality thermal oxide control samples. In addition there were no observable crystal defects induced within the underlying silicon, known to enhance dopant diffusion. However, we observed a high density of macroscopic surface defects (> 1.25 x 10^−12cm^−2) — believed to arise from spitting of silicon particles from the Si cell. These defects created leakage
paths in C-V and MOSFET devices and, despite reducing the device size to 2 x 10^−4cm^2, inhibited electrical optimisation of the oxide. Nevertheless, electrical characterisation of the oxide was possible for several samples and indicated a trap density of Nit < 4.3 x 10^11cm^−2, consistent with that of un-annealed thermal oxide control samples (Nit < 3 −6 x 10^11cm^−2).
The low temperature UHV silicon dioxide was then incorporated into a surface gated single electron transistor with 200 P donors, whose small size (< 1 x 10^−8cm^2) reduced the likelihood of overlap with macroscopic defects. The results were compared to an inplane gated SET of the same size, which did not have a surface gate. The surface gated SET showed gating up to electric fields of 1MV.cm^−1 —exceeding the range of all-epitaxial in-plane gates by around one order of magnitude (< 0.2MV.cm−1). Using the surface gate, we were able to tune the number of electrons on the dot by 160e, compared to 30e using a comparable in-plane gated device. Low-frequency noise measurements showed similar
charge noise using the two gating schemes (Qd = 0.5%e surface gated vs. 0.2%e in-plane gated), however there was severe hysteresis (4000e) in the gate action of the surface gated device. These results emphasise the greater tunability afforded by surface gated devices but highlight the need for further improvement of the low temperature dielectric.