Phase error reduction method for free-run QZSS clock

Abstract

A method for limiting the phase error of the remote time keeping system, RTKS, clock for the Japanese quasi-zenith satellite system (QZSS), is presented. To provide a proper positioning signal, QZSS satellites need stable on-board time references. Instead of using atomic references, the recently proposed RTKS employs a remote synchronization scheme that provides an opportune synchronization/correction signal able to keep a master time reference, located on the ground, and the QZSS satellite on-board time reference constantly in lock step. One of the critic issues regarding this architecture is the loss of synchronization due to satellite communication interruption. The proposed method consists of a learning algorithm that monitors the on-board clock behavior during its regular functioning. Consequently, when synchronization becomes unavailable the QZSS onboard clock phase/frequency drift is kept contained by using a consecutive estimation of the clock phase error. The proposed system is particularly suitable for the RTKS for QZSS and is characterized by a low hardware requirement profile, particularly suitable for the RTKS satellite payload.