Publication:
Rapid embedded hardware/software system generation
Rapid embedded hardware/software system generation
| dc.contributor.author | Peddersen, Jorgen | en_US |
| dc.contributor.author | Shee, Seng Lin | en_US |
| dc.contributor.author | Janapsatya, Andhi | en_US |
| dc.contributor.author | Parameswaran, Sri | en_US |
| dc.date.accessioned | 2021-11-25T13:00:44Z | |
| dc.date.available | 2021-11-25T13:00:44Z | |
| dc.date.issued | 2005 | en_US |
| dc.description.abstract | This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30%, energy consumed reduced by 24%, and performance improved by 24%. © 2005 IEEE. | en_US |
| dc.description.uri | http://www.informatik.uni-trier.de/~ley/db/conf/vlsid/vlsid2005.html | en_US |
| dc.identifier.isbn | 0769522645 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1959.4/38932 | |
| dc.language | English | |
| dc.language.iso | EN | en_US |
| dc.publisher | IEEE Computer society | en_US |
| dc.rights | CC BY-NC-ND 3.0 | en_US |
| dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
| dc.source | Legacy MARC | en_US |
| dc.subject.other | Embedded systems | en_US |
| dc.subject.other | Computer hardware | en_US |
| dc.subject.other | Computer software | en_US |
| dc.subject.other | C (programming language | en_US |
| dc.subject.other | Computer architecture | en_US |
| dc.subject.other | Program processors | en_US |
| dc.subject.other | Benchmarking | en_US |
| dc.title | Rapid embedded hardware/software system generation | en_US |
| dc.type | Conference Paper | en |
| dcterms.accessRights | open access | |
| dspace.entity.type | Publication | en_US |
| unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
| unsw.description.publisherStatement | © 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
| unsw.identifier.doi | https://doi.org/10.26190/unsworks/421 | |
| unsw.publisher.place | Los Alamitos, CA, USA | en_US |
| unsw.relation.faculty | Engineering | |
| unsw.relation.ispartofconferenceLocation | Kolkata, India | en_US |
| unsw.relation.ispartofconferenceName | 18th International Conference on VLSI Design (VLSI Design 2005) | en_US |
| unsw.relation.ispartofconferenceProceedingsTitle | Proceedings of VLSI Design 2005 | en_US |
| unsw.relation.ispartofconferenceYear | 2005 | en_US |
| unsw.relation.ispartofpagefrompageto | 111-116 | en_US |
| unsw.relation.originalPublicationAffiliation | Peddersen, Jorgen, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.originalPublicationAffiliation | Shee, Seng Lin, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.originalPublicationAffiliation | Janapsatya, Andhi, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.originalPublicationAffiliation | Parameswaran, Sri, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
| unsw.relation.school | School of Computer Science and Engineering | * |
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