Polar Codes Decoding Algorithms and FPGA-based Hardware Architectures

Abstract

As the first family of error correction codes that is theoretically proved to achieve channel capacity under successive cancellation (SC) decoder when code length tends to infinity, the polar coding scheme is regarded as a milestone in the information and coding theory. However, at finite code lengths, the SC decoder does not provide a satisfactory error correction performance compared to other codes such as low-density parity check (LDPC) codes. To overcome this weakness, various polar code constructions and decoding algorithms have been proposed. In this thesis, we first study all the significant developments in the field of polar coding covering 1) major signal-to-noise ratio (SNR)-dependent code constructions as well as universal reliability sequence, and 2) decoding algorithms including SC, SC list (SCL), cyclic redundancy check-aided SCL (CA-SCL), belief propagation (BP), and soft cancellation (SCAN) decoders. This study analyzes the performance and computational complexity of the available approaches to improve polar codes. Then, we turn our focus on Polarization-adjusted convolutional (PAC) codes which were recently proposed. These promising codes can further enhance the performance with (near) maximum likelihood (ML) decoders such as sequential decoders and sphere decoders. Convolutional precoding enables PAC codes to reduce the number of minimum-weight codewords of polar codes. Since this convolutional precoding cannot be employed with sphere decoding directly due to the direction of this decoding scheme as the lower rectangular shape of polar transform demands. We propose a selective reverse convolutional precoding scheme to reduce the error coefficient while avoiding the reduction in the minimum distance due to concatenation. The numerical results show that the proposed scheme can reduce the code’s error coefficient significantly resulting in improving the block error rate of polar codes under sphere decoding by up to 0.5 dB. Moreover, the hardware design of a decoding algorithm is considered. The memory requirement for the intermediate information in decoding algorithms takes a large silicon area, in particular belief propagation (BP) decoding. As an alternative to uniform quantization, we suggest employing a non-uniform quantization scheme that reduces the decoder’s memory requirement and improves its performance. To evaluate, we design a field programmable gate array (FPGA)-based hardware architecture for the BP decoder. A lookup table-based architecture is designed for the non-uniform quantization scheme to preserve the throughput. The design is verified on a development board. The numerical results reveal the expected performance improvement while reducing the memory requirement.