An FPGA Interpreter with Virtual Hardware Management Diessel, Oliver en_US Malik, Usama en_US 2021-11-25T13:27:11Z 2021-11-25T13:27:11Z 2002 en_US
dc.description.abstract This paper describes the design of an interpreter that overcomes FPGA resource limitations for a class of control-oriented circuits by automatically partitioning, elaborating, and loading circuit components as directed by their execution. By providing a virtual hardware management facility, this enables us to implement large systems, specified in Circal, on small FPGA chips. en_US
dc.description.uri en_US
dc.identifier.isbn 769515738 en_US
dc.language English
dc.language.iso EN en_US
dc.publisher IEEE Computer Society en_US
dc.rights CC BY-NC-ND 3.0 en_US
dc.rights.uri en_US
dc.source Legacy MARC en_US
dc.title An FPGA Interpreter with Virtual Hardware Management en_US
dc.type Conference Paper en
dcterms.accessRights open access
dspace.entity.type Publication en_US
unsw.description.publisherStatement ©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. en_US
unsw.identifier.doi Los Alamitos en_US
unsw.relation.faculty Engineering
unsw.relation.ispartofconferenceLocation Fort Lauderdale, USA en_US
unsw.relation.ispartofconferenceName International Parallel & Distributed Processing Symposium en_US
unsw.relation.ispartofconferenceProceedingsTitle 16th International Parallel & Distributed Processing Symposium en_US
unsw.relation.ispartofconferenceYear 2002 en_US
unsw.relation.ispartofpagefrompageto 155-162 en_US
unsw.relation.originalPublicationAffiliation Diessel, Oliver, Computer Science & Engineering, Faculty of Engineering, UNSW en_US
unsw.relation.originalPublicationAffiliation Malik, Usama en_US School of Computer Science and Engineering *
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