An Exploration of Entropy Sources in Standard CMOS for Cryptographic Applications

Abstract

This thesis represents a body of work regarding the design, implementation and test of a quantum entropy source in a commercially available semiconductor process. The techniques proposed have been designed to be process-agnostic, meaning that the work presented is highly transferable.

The analysis of literature provides the motivation for selecting a quantum mechanism as a noise generator to be utilised in an entropy source. Quantum tunnelling provides a non-deterministic rectifying process which mimics the statistics of a shot noise source which is a white Gaussian noise process that cannot be predicted by any analytical form. The dominance of Fowler Nordheim tunnelling at a high bias regime is assumed which allows for predictive small signal models and design equations to be formed.

Numerical data and device measurements are presented by utilising a metal oxide semiconductor (MOS) capacitor structure, realised by grounding the drain and source of a MOS transistor. The thin oxide layer between the gate-bulk and the gate-drain, and gate-source presents a potential barrier that provides ideal tunnelling conditions. Devices of varying sizes across multiple chips are fabricated and tested to characterise inter and intra-wafer variation. Additional effort is spent creating temperature dependence and defect models.

A methodology to utilise quantum tunnelling as a tool to extract series parasitic resistances is proposed and demonstrated, where by an analytical augmented model is able directly estimate the resistance value through either an analytical solution or parameter estimation techniques. This is verified with scattering parameter measurements in a practical experiment where the two methodologies produce almost identical results.

Entropy measurements of the collected data are tested against the NIST SP800-90B test suite and show promising pre-conditioning performance. Entropy rates of up to 0.716 bits per bit are demonstrated when operating in extended lifespan (bias current of 3.5mA) and up to 0.91 bits per bit at a maximum possible bias (4mA) for a device surface area of 52.2mm^2. The effects of sample rate, bit depth and ADC linearities on the total entropy are discussed.

It is concluded that additional research and implementation regarding sensing and measurement structures can greatly improve both the signal to noise ratio and bandwidth of the entropy source which in turn would result in a higher entropy rate.