Publication:
Instruction trace compression for rapid instruction cache simulation
Instruction trace compression for rapid instruction cache simulation
dc.contributor.author | Janapsatya, Andhi | en_US |
dc.contributor.author | Ignjatovic, Aleksandar | en_US |
dc.contributor.author | Parameswaran, Sri | en_US |
dc.contributor.author | Henkel, Joerg | en_US |
dc.date.accessioned | 2021-11-25T13:00:39Z | |
dc.date.available | 2021-11-25T13:00:39Z | |
dc.date.issued | 2007 | en_US |
dc.description.abstract | Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular application. To find the best cache size suited for a particular embedded system, the applications) is/are executed, traces obtained, and caches simulated. Typically, program trace files can range from a few megabytes to several gigabytes. Simulation of cache performance using large program trace files is a time consuming process. In this paper, a novel instruction cache simulation methodology that can operate directly on a compressed program trace file without the need for decompression is presented. This feature allowed our simulation methodology to have an average speed up of 9.67 times compared to the existing state of the art tool (Dinero IV cache simulator), for a range of applications from the Mediabench suite. © 2007 EDAA. | en_US |
dc.identifier.isbn | 9783981080124 | en_US |
dc.identifier.uri | http://hdl.handle.net/1959.4/38929 | |
dc.language | English | |
dc.language.iso | EN | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc., Piscataway, NJ 08855-1331, United States | en_US |
dc.rights | CC BY-NC-ND 3.0 | en_US |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/3.0/au/ | en_US |
dc.source | Legacy MARC | en_US |
dc.subject.other | Data compression | en_US |
dc.subject.other | Buffer storage | en_US |
dc.subject.other | Computer simulation | en_US |
dc.subject.other | Embedded systems | en_US |
dc.title | Instruction trace compression for rapid instruction cache simulation | en_US |
dc.type | Conference Paper | en |
dcterms.accessRights | open access | |
dspace.entity.type | Publication | en_US |
unsw.accessRights.uri | https://purl.org/coar/access_right/c_abf2 | |
unsw.description.publisherStatement | © 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | en_US |
unsw.identifier.doiPublisher | http://dx.doi.org/10.1109/DATE.2007.364389 | en_US |
unsw.relation.faculty | Engineering | |
unsw.relation.ispartofconferenceName | Design, Automation & Test in Europe Conference & Exhibition | en_US |
unsw.relation.ispartofconferenceProceedingsTitle | DATE 07 | en_US |
unsw.relation.ispartofconferenceYear | 2007 | en_US |
unsw.relation.ispartofpagefrompageto | 803-808 | en_US |
unsw.relation.originalPublicationAffiliation | Janapsatya, Andhi, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Ignjatovic, Aleksandar, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Parameswaran, Sri, Computer Science & Engineering, Faculty of Engineering, UNSW | en_US |
unsw.relation.originalPublicationAffiliation | Henkel, Joerg | en_US |
unsw.relation.school | School of Computer Science and Engineering | * |
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