Other UNSW

Publication Search Results

Now showing 1 - 2 of 2
  • (2020) O'Neill, Daniel
    This thesis examines the impacts of Electric Vehicles (EVs) and Vehicle-to-Grid (V2G) technology on residential microgrid environments. EVs are rapidly growing technology which play a major role in lowering Greenhouse-gas emissions in the transport sector. Additionally, EVs can also reduce emissions in the energy sector while also improving grid stability. This can be implemented by V2G technology supporting variable renewable generation (as additional storage) and by providing ancillary services. While some studies have presented specific instances of V2G implementation, long-term operation of the technology is still not well researched. Past research indicated financial barriers and availability as concerns which deter the implementation of V2G. Recent advancements in battery technology present new opportunities to make the technology viable. Using current and predicted EV technology trends, new EV load and V2G availability profiles were developed and used to evaluate the long-term operation and benefits of EVs and V2G in a residential microgrid environment. Simulation results indicate that the operation of V2G in a microgrid environment improves the economic operation of the system and reduces the levelized cost of energy by up to 5.7%. These results suggest the latest advancements in EV technology have improved the economic viability of V2G as well as its potential for further improving grid efficiency by providing energy services like peak demand shaving and additional storage capacity.

  • (2019) Yang, Edward
    Newer CMOS technologies allow for circuits to poses higher frequency performance, lower power consumption, reduced cost per transistor, and smaller layout area. Digital circuits greatly benefit from the use of newer CMOS technologies, but analogue circuits do not. In more modern CMOS technologies, the transconductance and output resistance of a transistor decrease, to which these two parameters serve as the foundation for developing high-performance analogue circuitry. The manufacturing process defines the transconductance of a transistor, but circuit techniques can make a transistor to seem like it has higher output resistance. The development and verification of a 22nm FDSOI CMOS op-amp and it’s supporting characterising circuit (the OPCC) are the two goals of this thesis. The process involves an investigation into various output resistance improve circuit techniques and finding methods to scale the circuit into a 22nm FDSOI CMOS process. A single-stage and a two-stage high-gain op-amp developed in a 22nm FDSOI CMOS process is presented. Two hundred runs of Monte Carlo simulations, which include transistor mismatch and process variation, validates the operation of the two op-amps. The integration of a modified high output resistance current mirror allows the op-amp to achieve high DC gains. The two-stage op-amp can perform rail-to-rail operations with a 800mV power supply voltage while driving a 1 pF capacitive load. The single-stage op-amp is simulated to have a 69 dB minimum DC gain, 29MHz UGB, with a PM of 86°. The two-stage op-amp is simulated to have a 103 dB minimum DC gain, 50MHz UGB, and a PM of 50°. Sequentially, a 22nm CMOS on-chip digitally controlled op-amp characterisation circuit is presented. The conversion of old on-chip and breadboard- based op-amp characterisation methods are scaled to the 22nm FDSOI CMOS process to enable the measurement of op-amps that are designed for on-chip use. Advancements in CMOS manufacturing process reduce the performance of transmission gates, to which, methods to mitigate the reduction in performance are elaborated. The OPCC enables the measurement of offset voltage with max SD of 0.1mV, input bias currents with max SD of 15.7pA, bandwidth with max SD of 1.73MHz, open-loop gain with max SD of 0.4 dB, CMRR with max SD of 8.774 dB, and PSRR with max SD of 1.1dB. Four hundred runs of Monte Carlo simulations validate the operations of the OPCC, which also indicates its potential implementation in older CMOS technologies.