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  • Communications Infrastructure Generation for Modular FPGA Reconfiguration
    (2006) Koh, Shannon; Diessel, Oliver
    Conference Paper
    Modules that are swapped dynamically at run-time on an FPGA have varying communication needs over time. In order to support this, we aim to generate a wiring infrastructure that caters for the dynamically-changing module interfaces. This, however, imposes a regular structure for laying out modules on a device, which may result in longer inter-module wiring paths as compared to traditional methods where the netlists are flattened. This paper studies placing modules within a structured layout to compare resulting circuit speeds with those obtained by traditional methods. Our results indicate that the difference in critical path delay is high at very low utilisation, but that the overhead is absorbed as the number of modules and interconnection density increases to realistic levels. The authors conclude that implementing such a wiring infrastructure has manageable overheads while having the added advantage of being amenable to dynamic reconfiguration.
  • COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs
    (2006) Koh, Shannon; Diessel, Oliver
    Conference Paper
    On-going improvements in the scaling of FPGA device sizes and time-to-market pressures encourage the use of module-oriented design flows [3], while economic factors favour the reuse of smaller devices for high performance computational tasks. One of the core problems in proposing dynamic modular reconfiguration approaches is supporting the differing communications needs of the sequence of modules configured over time [2]. Proposals to date have not focussed on communications issues. Moreover, they have advocated the use of specific protocols [4], or they cannot be readily implemented [1], or they suffer from high overheads [5], or rely upon deprecated features such as tri-state lines [7]. In contrast, we propose a methodology for the rapid deployment of a communications infrastructure that provides the wires required by dynamic modules and allows users to implement the protocols they want. Our aim is to support new tiled dynamically reconfigurable architectures such as Virtex-4, as well as mature device families.
  • The enotropy of FPGA reconfiguration
    (2006) Malik, Usama; Diessel, Oliver
    Conference Paper
    In line with Shannon's ideas, we define the entropy of FPGA reconfiguration to be the amount of information needed to configure a given circuit onto a given device. We propose using entropy as a gauge of the maximum configuration compression that can be achieved and determine the entropy of a set of 24 benchmark circuits for the Virtex device family. We demonstrate that simple off-the-shelf compression techniques such as Golomb encoding and hierarchical vector compression achieve compression results that are within 1-10% of the theoretical bound. We present an enhanced configuration memory system based on the hierarchical vector compression technique that accelerates reconfiguration in proportion to the amount of compression achieved. The proposed system demands little additional chip area and can be clocked at the same rate as the Virtex configuration clock.
  • Functional unit chaining: a runtime adaptive architecture for reducing bypass delays
    (2006) Koh, Lih; Diessel, Oliver
    Conference Paper
    Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affect the performance of sequential code sequences. We propose dealing with these delays through a dynamic functional unit chaining approach. We study the performance benefits of a superscalar, out-of-order processor augmented with a two-by-two array of ALUs interconnected by a fast, partial bypass network. An online profiler guides the automatic configuration of the network to accelerate specific patterns of dependent instructions. A detailed study of benchmark simulations demonstrates these first steps towards mapping binaries to a small coarse-grained array at runtime can improve instruction throughput by over 18% and 25% when the microarchitecure includes bypass delays of one cycle and two cycles, respectively.
  • Challenges and opportunities in LCA - the water industry example
    (2006) Peters, Greg M.; Rowley, Hazel; Lundie, S; Flint, Megan
    Conference Paper
    Challenges like population growth and climate change are maintaining a high level of dynamism in the water industry, resulting in large capital investments and the consideration of alternatives to conventional water supplies. In this environment, LCA is appreciated as a useful planning tool, but it has not yet achieved its full potential due to the lack of a national sustainability framework and other factors. In this paper, examples of recent LCAs in the water industry are discussed. The practical justification and resourcing of LCAs are examined. In addition, two case studies are presented illustrating how LCA can assist the planning process and the degree to which hybridisation presents a methodological challenge to traditional process LCA. Finally, the implications of the new WSAA Sustainability Framework for the future of LCA practice are discussed.
  • Model-driven benchmark generation for web services
    (2006) Zhu, Liming; Gorton, Ian; Liu, Yan; Bui, Bao
    Conference Paper
    Web services solutions are being increasingly adopted in enterprise systems. However, ensuring the quality of service of Web services applications remains a costly and complicated performance engineering task. Some of the new challenges include limited controls over consumers of a service, unforeseeable operational scenarios and vastly different XML payloads. These challenges make existing manual performance analysis and benchmarking methods difficult to use effectively. This paper describes an approach for generating customized benchmark suites for Web services applications from a software architecture description following a Model Driven Architecture (MDA) approach. We have provided a performance-tailored version of the UML 2.0 Testing Profile so architects can model a flexible and reusable load testing architecture, including test data, in a standards compatible way. We extended our MDABench [27] tool to provide a Web service performance testing “cartridge” associated with the tailored testing profile. A load testing suite and automatic performance measurement infrastructure are generated using the new cartridge. Best practices in Web service testing are embodied in the cartridge and inherited by the generated code. This greatly reduces the effort needed for Web service performance benchmarking while being fully MDA compatible. We illustrate the approach using a case study on the Apache Axis platform.
  • Learning causal networks from microarray data
    (2006) Bain, Michael; Ahsan, Nasir; Potter, John; Gaeta, Bruno; Temple, Mark; Dawes, Ian
    Conference Paper
  • Proceedings of ACUN-5 Developments in Composites: Advanced, Infrastructural, Natural, and Nano-Composites
    (2006) Bandyopadhyay, Srikanta; Zeng, Qinghua; Berndt, Christopher C.; Rizkalla, Sami; Gowripalan, N.; Matisons, Janis
    Conference Paper
    The topics of ACUN-5 will cover all aspects of the science and technology of composite materials, from materials fabrication, processing, manufacture, structural and property characterisation, theoretical analysis, modelling and simulation, materials design to a variety of applications, such as aerospace, automotive, infrastructure, packaging, ship-building, and recreational products. ACUN-5 will bring together the latest research and developments of the complete range of composite materials, including biocomposites, medical-composites, functional and smart composites, gradient and layered composites, nanocomposites, structural composites and mimicking natural materials. The reinforcements will range from nano-, micro-, meso- to macro-scale in polymer, metal, ceramic and cementitious matrices.
  • Protecting multicast sessions in wireless mesh networks
    (2006) Zhao, Xin; Chou, Chun; Guo, Jun; Jha, Sanjay
    Conference Paper
    To support reliable multicast routing in wireless mesh networks, it is important to protect multicast sessions against link or node failures. The issue of protecting multicast sessions in wireless mesh networks is a new problem to the best of our knowledge. In this paper, we propose a resilient forwarding mesh approach for protecting a multicast session in wireless mesh networks. Utilizing the wireless broadcast advantage, a resilient forwarding mesh effectively establishes two node disjoint paths for each source destination pair. This allows a multicast session to be immune from any single link or intermediate node failure. We introduce four heuristic algorithms to obtain approximate solutions that seek to minimize the number of required broadcast transmissions. We evaluate the performance of these heuristic algorithms against the optimal resilient forwarding mesh (ORFM) obtained by solving an integer linear programming (ILP) formulation of the problem. Experimental results demonstrate that one of these heuristic algorithms, which we call the minimal disjoint mesh algorithm (MDM), performs sufficiently close to ORFM. Besides, we find that the resilient forwarding mesh approach provides efficient 1+1 protection [8] to the multicast session without incurring much additional overhead on a single minimal cost multicast tree.