Engineering

Publication Search Results

Now showing 1 - 3 of 3
  • (2010) Cole, Fletcher; Cox, Shane; Frances, Maude
    Conference Paper
    An opportunity to explore the topic of data usages is presented by the collaborative research being undertaken by a federation of applied science research units affiliated with a number of different Australian research organizations (the Cluster). The research aims to investigate how members of the collaboration understand and work with data in their day-to-day practice.

  • (2018) Khaled, Mohammad
    Thesis
    The characteristic length of the thin film systems used nowadays in nanoscale thermoelectric and microelectric devices are comparable to the mean free path and wavelength of energy carriers. As a result, the application of classical theorise to characterise thermal transport at the nanoscale is questionable. However, it is essential to understand the underlying physics of heat propagation in thin film systems to control, manipulate, and manage thermal properties in micro and nanodevices. Understanding thermal properties by experiment are challenging, especially for materials with low thermal conductivity and small mean free path (MFP). On the other hand, molecular dynamics (MD) allows investigation of sophisticated crystalline, bulk, interface and surface effects of thermal conduction problem with accuracy, fidelity, and reliability. Nevertheless, the computational results of MD can suffer from the wrong choice of critical parameters, unfit empirical potentials for thermal application and provide unreliable thermal conductivity. Moreover, the dependence of the thermal boundary resistance (TBR) on temperature, thin film's dimension, and defects are not systematically assessed for the important thin films in the thermal application. To solve this problem, a systematic equilibrium molecular dynamics (EMD), addressing the critical issues in thermal conduction characterisation is proposed at the classical temperature range, where thermal conduction is dominated by phonons. The model has been validated by investigating the thermal conduction of Si and dielectrics used in thin film systems. The issue with empirical potential is addressed by critically assessing the performance of a potential on the basis of thermal conductivity, atomic energy and phonon density of state prediction. Later, thin film systems are studied to understand relative phonon propagation at the interface and quantify TBR's dependence on interface area, interfacial distance as well as temperature. Finally, the thermal resistance of thin film systems with defects is characterised to understand realistic phonon propagation scenario in the thermal application of thin film systems.

  • (2019) Yang, Edward
    Thesis
    Newer CMOS technologies allow for circuits to poses higher frequency performance, lower power consumption, reduced cost per transistor, and smaller layout area. Digital circuits greatly benefit from the use of newer CMOS technologies, but analogue circuits do not. In more modern CMOS technologies, the transconductance and output resistance of a transistor decrease, to which these two parameters serve as the foundation for developing high-performance analogue circuitry. The manufacturing process defines the transconductance of a transistor, but circuit techniques can make a transistor to seem like it has higher output resistance. The development and verification of a 22nm FDSOI CMOS op-amp and it’s supporting characterising circuit (the OPCC) are the two goals of this thesis. The process involves an investigation into various output resistance improve circuit techniques and finding methods to scale the circuit into a 22nm FDSOI CMOS process. A single-stage and a two-stage high-gain op-amp developed in a 22nm FDSOI CMOS process is presented. Two hundred runs of Monte Carlo simulations, which include transistor mismatch and process variation, validates the operation of the two op-amps. The integration of a modified high output resistance current mirror allows the op-amp to achieve high DC gains. The two-stage op-amp can perform rail-to-rail operations with a 800mV power supply voltage while driving a 1 pF capacitive load. The single-stage op-amp is simulated to have a 69 dB minimum DC gain, 29MHz UGB, with a PM of 86°. The two-stage op-amp is simulated to have a 103 dB minimum DC gain, 50MHz UGB, and a PM of 50°. Sequentially, a 22nm CMOS on-chip digitally controlled op-amp characterisation circuit is presented. The conversion of old on-chip and breadboard- based op-amp characterisation methods are scaled to the 22nm FDSOI CMOS process to enable the measurement of op-amps that are designed for on-chip use. Advancements in CMOS manufacturing process reduce the performance of transmission gates, to which, methods to mitigate the reduction in performance are elaborated. The OPCC enables the measurement of offset voltage with max SD of 0.1mV, input bias currents with max SD of 15.7pA, bandwidth with max SD of 1.73MHz, open-loop gain with max SD of 0.4 dB, CMRR with max SD of 8.774 dB, and PSRR with max SD of 1.1dB. Four hundred runs of Monte Carlo simulations validate the operations of the OPCC, which also indicates its potential implementation in older CMOS technologies.