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(2001)Journal ArticleThe development of FPGAs that can be programmed to implement custom circuits by modifying memory has inspired researchers to investigate how FPGAs can be used as a computational resource in systems designed for high performance applications. When such FPGA--based systems are composed of arrays of chips or chips that can be partially reconfigured, the programmable array space can be partitioned among several concurrently executing tasks. If partition sizes are adapted to the needs of tasks, then array resources become fragmented as tasks with varying requirements are processed. Tasks may end up waiting despite their being sufficient, albeit fragmented resources available. We examine the problem of repartitioning the system (rearranging a subset of the executing tasks) at run--time in order to allow waiting tasks to enter the system sooner. In this paper, we introduce the problems of identifying and scheduling feasible task rearrangements when tasks are moved by reloading. It is shown that both problems are NP--complete. We develop two very different heuristic approaches to finding and scheduling suitable rearrangements. The first method, known as Local Repacking, attempts to minimize the size of the subarray needing rearrangement. Candidate subarrays are repacked using known bin packing algorithms. Task movements are scheduled so as to minimize delays to their execution. The second approach, called Ordered Compaction, constrains the movements of tasks in order to efficiently identify and schedule feasible rearrangements. The heuristics are compared by time complexity and resulting system performance on simulated task sets. The results indicate that considerable scheduling advantages are to be gained for acceptable computational effort. However, the benefits may be jeopardized by delays to moving tasks when the average cost of reloading tasks becomes significant relative to task service periods. We indicate directions for future research to mitigate the cost of moving executing tasks.
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(2004)Journal ArticleWe present a hardware implementation of population-based ant colony optimization (P-ACO) on field-programmable gate arrays (FPGAs). The ant colony optimization meta-heuristic is adopted from the natural foraging behavior of real ants and has been used to find good solutions to a wide spectrum of combinatorial optimization problems. We describe the P-ACO algorithm and present a circuit architecture that facilitates efficient FPGA implementations. The proposed design shows modest space requirements but leads to a significant reduction in runtime over software-based solutions. Several modifications and extensions of the basic algorithm are also presented, including the approximation of the heuristic function by a small, dynamically changing set of favorable decisions.
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(2007)Conference PaperMinimising energy use is an important factor in the operation of many classes of embedded systems - in particular, battery-powered devices. Dynamic voltage and frequency scaling (DVFS) provides some control over a processor's performance and energy consumption. In order to employ DVFS for managing a system's energy use, it is necessary to predict the effect this scaling has on the system's total energy consumption. Simple (yet widely-used) energy models lead to dramatically incorrect results for important classes of application programs. Predicting the energy used under scaling requires (i) a prediction of the dependency of program performance (and hence duration of execution) on the frequencies and (ii) a prediction of the power drawn by the execution as a function of the frequencies and voltages. As both of these characteristics are workload-specific our approach builds a model that, given a workload execution at one frequency setpoint, will predict the run-time and power at any other frequency setpoint. We assume temporal locality (which is valid for the vast majority of applications) so predicting the characteristics of one time slice, frame, or other instance of a task, will imply the characteristics of subsequent time slices, frames or instances (e.g. MPEG video decoding). We present a systematic approach to building these models for a hardware platform, determining the best performance counters and weights. This characterisation, done once for a particular platform, produces platform-specific but workload-independent performance and power models. We implemented the model on a real system and evaluated it under a comprehensive benchmark suite against measurements of the actual energy consumption. The results show that the model can accurately predict the energy use of a wide class of applications and is highly responsive to changes in the application behaviour.
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(2006)Journal ArticleA parametrization of the density of states (DOS) near the band edge of phosphorus-doped crystalline silicon is derived from photoluminescence and conductance measurements, using a recently developed theory of band gap narrowing. It is shown that the dopant band only `touches` the conduction band at the Mott (metal-insulator) transition and that it merges with the conduction band at considerably higher dopant densities. This resolves well-known contradictions between conclusions drawn from various measurement techniques. With the proposed DOS, incomplete ionization of phosphorus dopants is calculated and compared with measurements in the temperature range from 300 to 30 K. We conclude that (a) up to 25% of dopants are nonionized at room temperature near the Mott transition and (b) there exists no significant amount of incomplete ionization at dopant densities far above the Mott transition. In a forthcoming part II of this paper, equations of incomplete ionization will be derived that are suitable for implementation in device simulators. (c) 2006 American Institute of Physics.
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(2006)Journal ArticleBuilding on Part I of this paper [Altermatt , J. Appl. Phys. 100, 113714 (2006)], the parametrization of the density of states and of incomplete ionization (ii) is extended to arsenic- and boron-doped crystalline silicon. The amount of ii is significantly larger in Si:As than in Si:P. Boron and phosphorus cause a similar amount of ii although the boron energy level has a distinctly different behavior as a function of dopant density than the phosphorus level. This is so because the boron ground state is fourfold degenerate, while the phosphorus ground state is twofold degenerate. Finally, equations of ii are derived that are suitable for implementation in device simulators. Simulations demonstrate that ii increases the current gain of bipolar transistors by up to 25% and that it decreases the open-circuit voltage of thin-film solar cells by up to 10 mV. The simulation model therefore improves the predictive capabilities of device modeling of p-n-junction devices.
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(2004)Journal ArticleIn this article we present the concept of a FPGA-based GPS receiver architecture with the aim of providing a framework for investigating new receiver architectures for current and upcoming GNSS standards. This development system facilitates researchers to prove new receiver concepts using real signals, which nowadays can only be simulated using tools such as Matlab. One will be able to work with the satellites as soon as they are operational, rather than having to wait for the availability of commercial products. The system allows individual development of signal processing solutions for base-band processing. A soft-core processor implements higher layer services that provide data to the user.
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(2003)Journal ArticleThe commonly used value of the intrinsic carrier density of crystalline silicon at 300 K is ni = 1.00×1010 cm–3. It was experimentally determined by Sproul and Green, J. Appl. Phys. 70, 846 (1991), using specially designed solar cells. In this article, we demonstrate that the Sproul and Green experiment was influenced by band-gap narrowing, even though the dopant density of their samples was low (1014 to 1016 cm–3). We reinterpret their measurements by numerical simulations with a random-phase approximation model for band-gap narrowing, thereby obtaining ni = 9.65×109 cm–3 at 300 K. This value is consistent with results obtained by Misiakos and Tsamakis, J. Appl. Phys. 74, 3293 (1993), using capacitance measurements. In this way, long-prevailing inconsistencies between independent measurement techniques for the determination of ni are resolved.
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(2002)Journal ArticleWe have established a simulation model for phosphorus-doped silicon emitters using Fermi–Dirac statistics. Our model is based on a set of independently measured material parameters and on quantum mechanical calculations. In contrast to commonly applied models, which use Boltzmann statistics and apparent band-gap narrowing data, we use Fermi–Dirac statistics and theoretically derived band shifts, and therefore we account for the degeneracy effects on a physically sounder basis. This leads to unprecedented consistency and precision even at very high dopant densities. We also derive the hole surface recombination velocity parameter Spo by applying our model to a broad range of measurements of the emitter saturation current density. Despite small differences in oxide quality among various laboratories, Spo generally increases for all of them in a very similar manner at high surface doping densities Nsurf. Pyramidal texturing generally increases Spo by a factor of five. The frequently used forming gas anneal lowers Spo mainly in low-doped emitters, while an aluminum anneal (Al deposit followed by a heat cycle) lowers Spo at all Nsurf.
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(2002)Journal ArticleWe assess a broad range of published experiments to show that the density of states (DOS) at high-energy grain boundaries in silicon is appropriately described by the defect-pool model. This implies that the DOS of such grain boundaries depends strongly on the dopant density and on the position of the Fermi level during device processing. However, since high-energy grain boundaries consist of an amorphous layer that is confined to a width of a few angstroms, the DOS is "frozen in" after material processing and does not suffer the strong degradation effects commonly observed in bulk a-Si:H. By combining three-dimensional device modeling and the defect-pool model, we reproduce various test structures and polycrystalline thin-film Si solar cells considerably more precisely than in the past. Our simulation model potentially provides a link between processing conditions and grain boundary quality.
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(2002)Journal ArticleWe have developed a three-dimensional numerical model of grain boundaries to simulate the electrical properties of polycrystalline silicon with doping densities larger than approximately 5×1017 cm–3. We show that three-dimensional effects play an important role in quantifying the minority-carrier properties of polycrystalline silicon. Our simulations reproduce the open-circuit voltage of a wide range of published experiments on thin-film silicon p-n junction solar cells, choosing a velocity parameter for recombination at the grain boundaries, S, in the order of 105–106 cm/s. The simulations indicate that, although S has been reduced by one order of magnitude over the last two decades, improvements in the open-circuit voltage have mainly been achieved by increasing the grain size. A few options are proposed to further reduce S.