Hardware Trojans mitigation in MPSoCs

Abstract

Multiprocessor System-on-Chip (MPSoC) has become necessary due to the billions of transistors available to the designer, the need for fast design turnaround times, and the power wall. Thus, present embedded systems are designed with MPSoCs, and one possible way MPSoCs can be realized is through Pipelined MPSoC (PMPSoC) architectures, which are used in applications from video surveillance to cryptosystems. In the past, the security of a system was considered as a software level problem where attacks come from software and their countermeasures were also software-based. However, with the increasing number of transistors on a chip and the power wall, a hardware system design chain involves many untrusted third parties. Malicious modifications (referred to as Hardware Trojans, or HTs) can be done to the third-party components without designers' knowledge.

Hardware Trojans (HTs) are a significant concern due to the damage caused by their stealth. An adversary could use HTs to extract secret information (data leakage), to modify functionality/data (functional modification), or make MPSoCs deny service. Detecting or preventing the activation of hardware Trojans is a challenging task. The mitigation techniques proposed in the literature cannot guarantee that the ICs are free from hardware Trojans.

This thesis presents online monitoring, checking, and testing methodologies to mitigate hardware Trojans with any triggering mechanism and with Data Leakage (DL), Functional/Data Modification (FM), or/and Denial of Service (DoS) payloads. Four different techniques are presented in this thesis.

In the first two chapters, mechanisms are proposed that (1) detect the presence of hardware Trojans in Third Party Intellectual Property (3PIP) cores of PMPSoCs, by continuous monitoring, and (2) recover the system by switching the infected processor core with another one. The first technique is to mitigate HTs with all three mentioned payloads, while in the second chapter, two different techniques for mitigating HTs with DoS payloads are presented. We designed, implemented, and tested the PMPSoCs on a commercial cycle-accurate multiprocessor simulation environment and showed that such a system could work in the presence of hardware Trojans.

In the second two chapters, online monitoring and testing mechanisms to (1) detect and identify HTs with FM and DoS payloads in general MPSoCs, and (2) recover the MPSoCs to keep its execution in the presence of HTs. These mechanisms use the concept of application-specific testing for runtime detection of HTs. The MPSoCs are designed and implemented on a real hardware platform (FPGA) to show the practicality and the effectiveness of these techniques.

Our experimental results show that the proposed HT mitigation techniques proposed in this thesis are effective to detect HT attacks, identify the infected component and isolate it, and finally recover the system from the attack. In comparison to the state-of-the-art mechanisms, the design's overheads (area and power consumption) are significantly lower.